1. FIELD OF THE INVENTION
The present invention relates to voltage-controlled oscillators, and more particularly to a gallium arsenide delay cell for a voltage-controlled ring oscillator, the propagation delay of which is controlled using a differential voltage-to-current converter.
2. ART BACKGROUND
In computer and other digital systems, it is often necessary to generate an internal clock signal the frequency of which is a multiple of the frequency of some externally available reference clock. A common manner of generating such an internal clock is to use a voltage-controlled ring oscillator, which is designed to oscillate at approximately the desired multiple of the frequency of the reference clock. The voltage controlled oscillator is then employed within a phase-locked loop circuit (PLL) to align the phase of the internally generated clock with the reference clock.
FIG. 1 illustrates a typical PLL block diagram. Voltage-controlled oscillator 14 is designed to generate a periodic signal 19 having a frequency range which includes the desired multiple of the frequency of a reference signal 15. A frequency divider 16 divides the generated signal 19 by the desired multiple to obtain a signal 13 having a frequency within some range of the frequency of the reference signal 15. A phase detector 10 senses any difference between the reference signal 15 and the divided signal 13 and provides an error voltage (V.sub.e) 11 which is directly proportional to the detected phase difference. This error voltage is then filtered by high-pass filter 12 to eliminate the D.C. component from V.sub.e, which serves to slow down the error voltage response. The filtered voltage becomes a control voltage V.sub.c 18 which is coupled to a control tap of the voltage-controlled oscillator (VCO) 14. The control V.sub.c 18 adjusts the frequency of oscillation to bring the phase of the generated signal 19 into phase alignment with that of the reference signal 15. The exact frequency of the VCO 14 depends, preferably linearly, on V.sub.c 18. The feedback eventually drives V.sub.e to zero.
The VCO 14 is typically implemented as a ring oscillator as illustrated in FIG. 2. The delay through each stage 20 is varied by the common control voltage V.sub.c 18. The delay through each stage 20 is D, which equals D.sub.o +k.multidot.V.sub.c. The phase shift around the oscillator must be 180.degree. at DC. When the ring oscillator is operating, the phase shift around the ring will be 360.degree.. Thus, there will be an additional phase shift of 180.degree. due to the delay of each stage. For a ring oscillator implemented as shown in FIG. 1, the delay through each stage will therefore be equivalent to 45.degree. of phase shift. The frequency of oscillation of the ring oscillator of FIG. 2 can be calculated as F=1/(2.times.N.times.D), where N is the number of stages 20, and D is the delay of each stage. If F.sub.o is defined as the frequency of the oscillator when there is zero control voltage, it can be expressed as 1/(2.times.N.times.D.sub.o). The frequency of the oscillator can then be defined as F.sub.o /(1+k.multidot.V.sub.c /D.sub.c) which is approximately equal to F.sub.o (1-k.multidot.V.sub.c /D.sub.c). Thus, the frequency of the voltage-controlled oscillator will vary linearly with the control voltage V.sub.c, provided that the delay of each stage varies linearly with the control voltage.
For integrated circuit implementations of PLLs, it is often desirable for the control voltage of the VCO to be a fully differential signal, such that its common-mode value is ignored with respect to its differential value. A standard implementation for a delay stage suitable for implementing a ring oscillator type VCO is shown in FIG. 3. This delay stage consists of at least three source-coupled field-effect transistor (FET) logic (SCFL) cells. The cell operates by providing two paths by which a signal may propagate from differential input A to differential output Y, depending upon the value of the differential select input S. The minimum delay occurs when path A1 is fully selected by multiplexer 32, while the maximum delay occurs when path A0 is fully selected by multiplexer 32. Multiplexer 32 is designed to proportionally add the slow path A0 with the fast path A1 by permitting the select input S to vary continuously between a minimum and maximum value. Thus, the control voltage V.sub.c for this type of delay stage is the select input S. The range of the delay is set by the difference in delay between the slow and fast paths.
There are a number of disadvantages to the delay cell of FIG. 3. One is that multiplexer 32 is not able to proportionally add the slow delay to the fast delay in a completely linear manner. This is primarily due to the fact that the gain from the select signal S to the output Y is high near the transition point where the differential value S is 0, but decreases (i.e., saturates) as the select S approaches a differential voltage which selects only one path or the other. The result of this non-linear variation in delay with respect to control voltage is a non-linear variation in output frequency of the VCO versus control voltage. A second drawback of this cell is the presence of two separate signal paths (i.e., A0 or A1) through each delay stage 20 of a ring oscillator implemented using this delay cell, which leads to multiple signal paths around the ring oscillator. This in turn can lead to multiple modes of oscillation existing at the same time. A third drawback is that each delay stage requires at least three SCFL logic gates, which uses great chip area than a single gate delay cell.
FIG. 4 illustrates a simpler single-gate delay cell which can be implemented in technologies such as CMOS, which has the advantage of easy p-channel device fabrication. P-channel device 30 and n-channel device 32 are coupled to a control voltage which vary the resistance of those devices such that they can increase or decrease the time necessary for a signal on input 36 to reach output 34. The problem with this delay cell is that it is not implementable in gallium arsenide (GaAs) semiconductor technology. GaAs semiconductor technology does not readily permit fabrication of p-channel devices.
FIG. 5 illustrates a single-gate SCFL delay cell which provides the benefit of differential signals, but which also relies on the use of p-channel pull-up devices 50 to vary the propagation delay through the cell. The delay will be proportional to the resistance value of the p-channel and the capacitance of the gate of source follower devices 52. Thus, this would also not be a viable solution for implementation in a GaAs fabrication technology.
Thus, there is a need for a delay cell, preferably one that is inherently linear, is a single gate and provides differential signals, for implementation in GaAs semiconductor technology.